Electrically erasable programmable read only memory (EEPROM) is non-volatile memory (NVM) with a small number of individually erasable bytes (typically of the order of 8 bytes or less) that is often embedded within a micro controller. The micro controller generally also comprises a central processing unit (CPU) executing the application software. NVM requires high operational voltages, typically of the order of 10V-15V. However, the transistors used in an NVM circuit are also required to generate and route much higher voltages to the memory cells, as compared to the voltages required to operate normal logic transistors or random access memory (RAM) cells.
Thus, the relative cost of implementing NVM on an integrated circuit, otherwise referred to as a ‘chip’, is much higher than the costs associated with using normal logic and random access memory (RAM) circuits. This is especially the case when the number of individually erasable bytes is small, as in the case of an EEPROM. Here, the number of erasable bytes is heavily affected by these cost implications, due to the aforementioned need to provide a large number of bulky high-voltage transistors to support the NVM circuit.
To clarify this effect, it can be shown that in 0.25 μm Split-Gate-Flash (SGF) technology, a 4 KByte EEPROM (i.e. a 1024*4 byte erase sector size) requires a similar area to a large 128 KByte Flash memory block (i.e. a 128*1024 byte erase sector size). Furthermore, if this comparison is extended to 0.18 μm or 0.13 μm technologies, this effect is even greater, since the area to store one bit (bit-cell) for these technologies becomes relatively smaller than the surrounding high voltage logic.
Thus, most semiconductor manufacturers no longer provide on-chip EEPROMs. Instead, semiconductor manufacturers tend to now use Flash memory to emulate the operation of EEPROM, as shown in the process illustrated in FIG. 1.
Referring now to FIG. 1, a flowchart 100 illustrates a known operation of an EEPROM. All access to EEPROM variables is performed via an EEPROM driver subroutine, as shown in step 105. One operation of the EEPROM driver subroutine checks whether a program or erase operation is being performed by a CPU of the micro controller, as in step 110.
If a program or erase operation of a corresponding NVM is being performed by the CPU when one or more EEPROM variable(s) is/are being accessed, then the CPU determines whether the NVM allows the program or erase operation to be aborted, as shown in step 115. If the CPU determines that the NVM allows the program or erase operation to be aborted, in step 115, the program or erase operation is aborted, in step 120. The accessed variable is then read from EEPROM, as shown in step 125. Thereafter, the program or erase subroutine returns to normal operation, as in step 130.
However, if the CPU determines that the NVM does not allow the program or erase operation to be aborted, in step 115, the EEPROM variable being accessed is cached in, say, a normal (flash) random access memory (RAM) coupled to the NVM. The caching operation is typically controlled by driver software within the CPU, as shown in step 135.
In this manner, a complex EEPROM management operation is, in effect, required, and used to store data in and retrieve data from the large flash memory; the data being EEPROM variables.
A problem with this approach is that if the NVM allows the aborting of one or more program or erase operations, those operations must then be repeated. This requires additional Program/Erase cycles to be implemented by the CPU, thereby resulting in an earlier wear-out of the NVM.
Furthermore, if one or more program or erase operations cannot be aborted, either the software must wait several milliseconds until the one or more program or erase operations is/are completed or the data must be cached, thereby requiring additional RAM space. Furthermore, the caching operation itself requires valuable processing time.
A yet further problem with the known implementations is that the CPU is unable to access the flash memory for reading or writing functions if an erase operation (typically, several msec.) or program operation (typically, several μsec.) is pending.
The aforementioned problems make the handling of reading or writing operations of an EEPROM in a multi-tasking system both complex and inefficient. Thus, a need exists for an electronic device with improved EEPROM usage and method of operation therefor.